基于FPGA的200W像素CMOS摄像头采集显示

资源描述本实例使用美光的 CMOS 摄像头 MT9D111，它是美光的一款在单芯片系统上集成了一个先进的 200 万像素图像传感器和功能大的图像处理技术芯片。单芯片系统中的自动特性可以调整各种参数，以便在各种光照条件下拍摄到优质图像。 本例程的 FPGA 内部实现功能框图如图所示。上电初始， FPGA 需要通过 IIC 接口协议对摄像头模块进行寄存器初始化配置。这个初始化的基本参数，如初始化地址和数据存储在一个预先配置好的 FPGA 内嵌 ROM 中。

vip_ex9_new
vlgsrc
output_files
greybox_tmp
ddr2_high_performance_controller-library
db
altmemphy-library
alt_mem_ddrx_addr_cmd.v
alt_mem_ddrx_addr_cmd_wrap.v
alt_mem_ddrx_arbiter.v
alt_mem_ddrx_buffer.v
alt_mem_ddrx_buffer_manager.v
alt_mem_ddrx_burst_gen.v
alt_mem_ddrx_burst_tracking.v
alt_mem_ddrx_cmd_gen.v
alt_mem_ddrx_controller.v
alt_mem_ddrx_controller_st_top.v
alt_mem_ddrx_csr.v
alt_mem_ddrx_dataid_manager.v
alt_mem_ddrx_ddr2_odt_gen.v
alt_mem_ddrx_ddr3_odt_gen.v
alt_mem_ddrx_define.iv
alt_mem_ddrx_ecc_decoder.v
alt_mem_ddrx_ecc_decoder_32_syn.v
alt_mem_ddrx_ecc_decoder_64_syn.v
alt_mem_ddrx_ecc_encoder.v
alt_mem_ddrx_ecc_encoder_32_syn.v
alt_mem_ddrx_ecc_encoder_64_syn.v
alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
alt_mem_ddrx_fifo.v
alt_mem_ddrx_input_if.v
alt_mem_ddrx_list.v
alt_mem_ddrx_lpddr2_addr_cmd.v
alt_mem_ddrx_mm_st_converter.v
alt_mem_ddrx_odt_gen.v
alt_mem_ddrx_rank_timer.v
alt_mem_ddrx_rdata_path.v
alt_mem_ddrx_rdwr_data_tmg.v
alt_mem_ddrx_sideband.v
alt_mem_ddrx_tbp.v
alt_mem_ddrx_timing_param.v
alt_mem_ddrx_wdata_path.v
alt_mem_phy_defines.v
data_source.v
ddr2_controller.bsf
ddr2_controller.html
ddr2_controller.ppf
ddr2_controller.qip
ddr2_controller.v
ddr2_controller_advisor.ipa
ddr2_controller_alt_mem_ddrx_controller_top.v
ddr2_controller_bb.v
ddr2_controller_controller_phy.v
ddr2_controller_example_driver.v
ddr2_controller_example_top.sdc
ddr2_controller_example_top.v
ddr2_controller_example_top.v.tmp2
ddr2_controller_example_top_1.v
ddr2_controller_example_top_2.v
ddr2_controller_ex_lfsr8.v
ddr2_controller_phy.bsf
ddr2_controller_phy.html
ddr2_controller_phy.qip
ddr2_controller_phy.v
ddr2_controller_phy_alt_mem_phy.v
ddr2_controller_phy_alt_mem_phy_pll.qip
ddr2_controller_phy_alt_mem_phy_pll.v
ddr2_controller_phy_alt_mem_phy_pll.v_.bak
ddr2_controller_phy_alt_mem_phy_pll_bb.v
ddr2_controller_phy_alt_mem_phy_seq.vhd
ddr2_controller_phy_alt_mem_phy_seq_wrapper.v
ddr2_controller_phy_autodetectedpins.tcl
ddr2_controller_phy_bb.v
ddr2_controller_phy_ddr_pins.tcl
ddr2_controller_phy_ddr_timing.sdc
ddr2_controller_phy_ddr_timing.tcl
ddr2_controller_phy_report_timing.tcl
ddr2_controller_phy_report_timing_core.tcl
ddr2_controller_phy_summary.csv
ddr2_controller_pin_assignments.tcl
flash_avalon.v
flash_controller_hw.tcl
flash_controller_hw.tcl~
flash_ctrl.v
flash_top.v
iic_initrom.qip
iic_initrom.v
iic_initrom_bb.v
iic_initrom_inst.v
lcd_controller.v
lcd_controller_hw.tcl
lcd_controller_hw.tcl~
onchipram_for_ddr.qip
onchipram_for_ddr.v
onchipram_for_ddr_bb.v
onchipram_for_ddr_inst.v
onchipram_for_ddr_syn.v
PLLJ_PLLSPE_INFO.txt
pll_controller.ppf
pll_controller.qip
pll_controller.v
pll_controller_bb.v
pll_controller_inst.v
qmegawiz_errors_log.txt
rdfifo_for_sdram.qip
rdfifo_for_sdram.v
rdfifo_for_sdram_bb.v
rdfifo_for_sdram_inst.v
stp1.stp
video_fifo.qip
video_fifo.v
video_fifo_bb.v
video_fifo_inst.v
vip.out.sdc
vip.qpf
vip.qsf
vip.qws
vipled.map
vip_qsys.bsf
vip_qsys.cmp
vip_qsys.html
vip_qsys.qsys
vip_qsys.sopcinfo
wrfifo_for_sdram.qip
wrfifo_for_sdram.v
wrfifo_for_sdram_bb.v
wrfifo_for_sdram_inst.v