资 源 简 介
dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
文 件 列 表
clock
automake.log
clock.bld
clock.gyd
clock.jed
clock.jhd
clock.jid
clock.mfd
clock.ngc
clock.ngd
clock.npl
clock.pnx
clock.prj
clock.ptf
clock.rpt
clock.syr
clock.ucf
clock.v
clock.vm6
clock.xst
clock_ngdbuild.nav
clock._prj
last_used.ucf
ngdbuild.rsp
tmperr.err
_chipview.tcl
_cpldfit.rsp
_cpldfit.tcl
_impact.log
_ngdbld.rsp
__clock_2prj_exewrap.rsp
__impact.rsp
__projnav.log
_ngo
netlist.lst
_ngo
