《可综合的Verilog语法》国外著名大学老师编写，对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.
SHOW FULL COLUMNS FROM `jrk_downrecords` [ RunTime:0.001325s ]
SELECT `a`.`aid`,`a`.`title`,`a`.`create_time`,`m`.`username` FROM `jrk_downrecords` `a` INNER JOIN `jrk_member` `m` ON `a`.`uid`=`m`.`id` WHERE `a`.`status` = 1 GROUP BY `a`.`aid` ORDER BY `a`.`create_time` DESC LIMIT 10 [ RunTime:0.092111s ]
SHOW FULL COLUMNS FROM `jrk_tagrecords` [ RunTime:0.001259s ]
SELECT * FROM `jrk_tagrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 20 [ RunTime:0.001895s ]
SHOW FULL COLUMNS FROM `jrk_member` [ RunTime:0.001231s ]
SELECT `id`,`username`,`userhead`,`usertime` FROM `jrk_member` WHERE `status` = 1 ORDER BY `usertime` DESC LIMIT 10 [ RunTime:0.003579s ]
SHOW FULL COLUMNS FROM `jrk_searchrecords` [ RunTime:0.001135s ]
SELECT * FROM `jrk_searchrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 5 [ RunTime:0.003222s ]
SELECT aid,title,count(aid) as c FROM `jrk_downrecords` GROUP BY `aid` ORDER BY `c` DESC LIMIT 10 [ RunTime:0.015163s ]
SHOW FULL COLUMNS FROM `jrk_articles` [ RunTime:0.001404s ]
UPDATE `jrk_articles` SET `hits` = 1 WHERE `id` = 296308 [ RunTime:0.001325s ]
