资 源 简 介
verilog，4、5分频器，5分频器占空比3：2-Verilog, 4,5 dividers, five dividers ratio of 3:2
文 件 列 表
fen
work
fen
xst
_ngo
transcript
fen.npl
fen.v
fen.dhp
fen_map.ngm
__projnav.log
automake.log
fen_test.v
fen.bld
fen.ngd
fen_fen_test_v_tf.udo
fen_fen_test_v_tf.fdo
vsim.wlf
fen.prj
fen.par
fen.cmd_log
fen.syr
fen.ncd
fen_vhdl.prj
fen.lso
fen.xlate_nlf
fen.ngr
fen_map.ncd
fen.pcf
fen.ngc
fen.stx
fen_translate.nlf
fen.nc1
.untf
fen.ucf
fen.xpi
fen.lfp
_pace.ucf
fen_pad.csv
fen.pad
fen.ucf.untf
fen_translate.v
fen.versim_xlate
fen_last_par.ncd
fen_pad.txt
fen.ngm
fen.placed_ncd_tracker
fen.routed_ncd_tracker
fen.twr
fen.twx
fen.bgn
fen.drc
fen.bit
_impact.log
_impact.cmd
CC.mcs
AB.mcs
fen.pad_txt
AB.prm
AB.sig
fen_map.nlf
fen_map.sdf
fen.ut
bitgen.ut
fen_fen_test_v_tf.ndo
fen_map.v
fen.versim_map
fen.map_nlf
fen_fen_test_v_tf.mdo
fen_timesim.nlf
fen_timesim.sdf
fen_timesim.v
dd.mcs
coregen.log
coregen.prj
fen.versim_par
fen.par_nlf
fen_fen_test_v_tf.tdo
CC.prm
CC.sig
fen.mrp
dd.prm
dd.sig
__projnav
createTF.err
__projnav
