资 源 简 介
这是用verilog语言编写的可变量程数字频率计程序，可选择不同量程，下载到FPGA后现象正确。This is the Verilog language with a variable range digital frequency program, can choose a different range, download to the FPGA after the correct phenomenon。
文 件 列 表
verilog数字频率计
anjian.bsf
anjian.v
anjian.vwf
CNT.bsf
count.bsf
count.v
count.v.bak
D5.bsf
D5.v
db
div4.v
fen_pin_qi.bsf
fen_pin_qi.v
huandang.bsf
huandang.v
huandang.v.bak
incremental_db
kebianliangchengjishuqi.asm.rpt
kebianliangchengjishuqi.bdf
kebianliangchengjishuqi.done
kebianliangchengjishuqi.dpf
kebianliangchengjishuqi.fit.rpt
kebianliangchengjishuqi.fit.smsg
kebianliangchengjishuqi.fit.summary
kebianliangchengjishuqi.flow.rpt
kebianliangchengjishuqi.map.rpt
kebianliangchengjishuqi.map.smsg
kebianliangchengjishuqi.map.summary
kebianliangchengjishuqi.pin
kebianliangchengjishuqi.pof
kebianliangchengjishuqi.qpf
kebianliangchengjishuqi.qsf
kebianliangchengjishuqi.qws
kebianliangchengjishuqi.sof
kebianliangchengjishuqi.tan.rpt
kebianliangchengjishuqi.tan.summary
kebianliangchengjishuqi_assignment_defaults.qdf
lpm_ff0.bsf
lpm_ff0.inc
lpm_ff0.qip
lpm_ff0.tdf
lpm_ff5.v
pregate.bsf
pregate.v
pregate.v.bak
segdisplay.bsf
segdisplay.v
segdisplay.v.bak
xinhao.bsf
xinhao.v
xinhao.v.bak
