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UART_verilog, designed to send and receive asynchronous serial. Including the te...

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资 源 简 介

UART_verilog,自己设计的异步串行收发。包括测试文件。-UART_verilog, designed to send and receive asynchronous serial. Including the test file.

文 件 列 表

ST16C550.v
testbench.v
transmit.v
FIFO.v
receive.v
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