资 源 简 介
24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
文 件 列 表
Time
db
cmp_state.ini
Divider.bdf
Divider.bsf
fenpin.bdf
fenpin.bsf
fenpin1m.bsf
hour.bdf
hour.bsf
minute.bdf
minute.bsf
second.bdf
second.bsf
test.bdf
test.vwf
time.asm.rpt
time.bdf
time.done
time.fit.eqn
time.fit.rpt
time.fit.summary
time.fld
time.flow.rpt
time.map.eqn
time.map.rpt
time.map.summary
time.pin
time.pof
time.qpf
time.qsf
time.qws
time.sim.rpt
time.sof
time.tan.rpt
time.tan.summary
time10.bdf
time10.bsf
time10.vwf
time2.bdf
time2.bsf
time24.vwf
time4.bdf
time4.bsf
time4.vwf
time6.bdf
time6.bsf
