资 源 简 介
用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0
文 件 列 表
实战训练15 基于NIOSII处理器的数字钟设计
niosii_c_sim
niosii_c_generation_script
button_pio.v
cmp_state.ini
cpu.ocp
cpu.v
cpu.vo
cpu_0.ocp
cpu_0.v
cpu_0.vo
cpu_0_jtag_debug_module.v
cpu_0_jtag_debug_module_wrapper.v
cpu_0_ociram_default_contents.mif
cpu_0_test_bench.v
cpu_jtag_debug_module.v
cpu_jtag_debug_module_wrapper.v
cpu_ociram_default_contents.mif
cpu_test_bench.v
delay_reset_block.bdf
jtag_uart.v
jtag_uart_0.v
lcd_16207_0.v
led_pio.v
lpm_counter0.bsf
lpm_counter0.v
lpm_counter0_wave0.jpg
lpm_counter0_waveforms.html
niosii_c.bsf
niosii_c.ptf
niosii_c.v
niosii_c_log.txt
niosii_c_setup_quartus.tcl
onchip_ram_4K.v
onchip_ram_4K_test_component.v
pio_0.v
pio_1.v
pll.bsf
pll.v
rf_ram.mif
sdram.v
sdram_test_component.v
sopc_builder_debug_log.txt
sopc_led.bdf
sopc_led.qpf
sopc_led.qsf
sopc_led.qws
sysid.v
sysy_clk_timer.v
uart.v
uart_0.v
