资 源 简 介
2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-2-way video PDH" s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
文 件 列 表
F7-2VT-1DR
db
clk_div.bsf
clk_div.vhd
clk_div.vwf
CMI_DECODE1.bdf
CMI_DECODE1.bsf
CMI_ENCODE.bdf
CMI_ENCODE.bsf
counter.vhd
DESCR.bdf
DESCR.bsf
EN_8B10B.bsf
en_8b10b.vhd
F7-2VT-1DR.asm.rpt
F7-2VT-1DR.bdf
F7-2VT-1DR.cdf
F7-2VT-1DR.done
F7-2VT-1DR.fit.rpt
F7-2VT-1DR.fit.summary
F7-2VT-1DR.flow.rpt
F7-2VT-1DR.map.rpt
F7-2VT-1DR.map.summary
F7-2VT-1DR.pin
F7-2VT-1DR.pof
F7-2VT-1DR.qpf
F7-2VT-1DR.qsf
F7-2VT-1DR.qws
F7-2VT-1DR.sim.rpt
F7-2VT-1DR.tan.rpt
F7-2VT-1DR.tan.summary
F7-2VT-1DR.vwf
F7-2VT-1DR_description.txt
mux2_1.bsf
mux2_1.vhd
mux2_1.vwf
OTHER.bsf
OTHER.vhd
SCR.bdf
SCR.bsf
TX.bdf
tx_mux_module.bsf
tx_mux_module.vhd
