详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE
SHOW FULL COLUMNS FROM `jrk_downrecords` [ RunTime:0.001321s ]
SELECT `a`.`aid`,`a`.`title`,`a`.`create_time`,`m`.`username` FROM `jrk_downrecords` `a` INNER JOIN `jrk_member` `m` ON `a`.`uid`=`m`.`id` WHERE `a`.`status` = 1 GROUP BY `a`.`aid` ORDER BY `a`.`create_time` DESC LIMIT 10 [ RunTime:0.089361s ]
SHOW FULL COLUMNS FROM `jrk_tagrecords` [ RunTime:0.001302s ]
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SHOW FULL COLUMNS FROM `jrk_member` [ RunTime:0.001223s ]
SELECT `id`,`username`,`userhead`,`usertime` FROM `jrk_member` WHERE `status` = 1 ORDER BY `usertime` DESC LIMIT 10 [ RunTime:0.003590s ]
SHOW FULL COLUMNS FROM `jrk_searchrecords` [ RunTime:0.001045s ]
SELECT * FROM `jrk_searchrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 5 [ RunTime:0.003200s ]
SELECT aid,title,count(aid) as c FROM `jrk_downrecords` GROUP BY `aid` ORDER BY `c` DESC LIMIT 10 [ RunTime:0.014692s ]
SHOW FULL COLUMNS FROM `jrk_articles` [ RunTime:0.001267s ]
UPDATE `jrk_articles` SET `hits` = 1 WHERE `id` = 140766 [ RunTime:0.001256s ]
