文 件 列 表
8051core-Verilog
transcript
Make
Acc.v
All.v
Alu.v
alu_src1_sel.v
alu_src2_sel.v
alu_src3_sel.v
Comp.v
cy_select.v
Decoder.v
Defines.v
Divide.v
Dptr.v
ext_addr_sel.v
immediate_sel.v
IndiAddr.v
Multiply.v
op_select.v
Pc.v
Port_out.v
Psw.v
Ram.v
ram_rd_sel.v
Ram_sel.v
ram_wr_sel.v
Reg1.v
Reg2.v
Reg3.v
Reg4.v
Reg5.v
Reg8.v
Reg8r.v
Rom.v
rom_addr_sel.v
Sp.v
Tb_all.v
