文 件 列 表
Makefile
readme.txt
Verilog
alu.v
basic.asm
BASIC.HEX
basic.rom
cpu.v
dds.asm
DDS.HEX
dds.rom
dram.v
exp.v
hex2v
hex2v.c
idec.v
pram.v
regs.v
runit
sindata.c
sindata.hex
test.v
VHDL
ramlib_quartus.vhd
ramlib_sim.vhd
ramlib_xil.vhd
www
freerisc8_legal.htm
images
index.htm
risc8a.gif
risc8a_small.gif
risc8_manual.htm
_borders
_derived
_fpclass
_overlay
_private
_themes
_vti_cnf
_vti_pvt
