Verilog Behavioral Simulator (VBS):
Interpreted hardware simulator
Verilog Hardware Description Language
Behavioral design descriptions only
Scripting language support through SWIG
Implemented with portable C/C++
Optional support for a Verilog pre-processor (VBPP)
SHOW FULL COLUMNS FROM `jrk_downrecords` [ RunTime:0.002201s ]
SELECT `a`.`aid`,`a`.`title`,`a`.`create_time`,`m`.`username` FROM `jrk_downrecords` `a` INNER JOIN `jrk_member` `m` ON `a`.`uid`=`m`.`id` WHERE `a`.`status` = 1 GROUP BY `a`.`aid` ORDER BY `a`.`create_time` DESC LIMIT 10 [ RunTime:0.086409s ]
SHOW FULL COLUMNS FROM `jrk_tagrecords` [ RunTime:0.002355s ]
SELECT * FROM `jrk_tagrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 20 [ RunTime:0.001933s ]
SHOW FULL COLUMNS FROM `jrk_member` [ RunTime:0.002374s ]
SELECT `id`,`username`,`userhead`,`usertime` FROM `jrk_member` WHERE `status` = 1 ORDER BY `usertime` DESC LIMIT 10 [ RunTime:0.003846s ]
SHOW FULL COLUMNS FROM `jrk_searchrecords` [ RunTime:0.005108s ]
SELECT * FROM `jrk_searchrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 5 [ RunTime:0.003285s ]
SELECT aid,title,count(aid) as c FROM `jrk_downrecords` GROUP BY `aid` ORDER BY `c` DESC LIMIT 10 [ RunTime:0.015296s ]
SHOW FULL COLUMNS FROM `jrk_articles` [ RunTime:0.002697s ]
UPDATE `jrk_articles` SET `hits` = 1 WHERE `id` = 89810 [ RunTime:0.001271s ]
