卷积码编码viterbi译码算法FPGA实现工程

卷积码编码采用2,1,2非系统卷积码，译码算法采用viterbi算法，绝对工程验证，系统实现；最高支持50Mbit/s以上吞吐量

EncodeDecode
viterbi-library
simulation
reed_solomon-library
output_files
nco-library
iptb_viterbi_temp8240489537487339581
iptb_viterbi_temp7905970706934754523
iptb_viterbi_temp6521564995339949539
iptb_viterbi_temp380676208780334253
iptb_viterbi_temp2902082468568016575
iptb_viterbi_temp2236233685380176526
iptb_reed_solomon_temp3897698622544193818
incremental_db
greybox_tmp
a_rcvsym.txt
a_txsym.txt
BER_report.txt
block_period_stim.txt
check_uw.v
check_uw.v.bak
CodeRefDesignTop.v
CodeRefDesignTop.v.bak
code_rx.v
code_rx.v.bak
code_sample_mod.v
code_sample_mod.v.bak
code_tx.v
code_tx.v.bak
code_tx_fifo.qip
code_tx_fifo.v
code_tx_fifo_bb.v
convolutional_213_encode.v
convolutional_213_encode.v.bak
convolutional_code.v
convolutional_code.v.bak
convolutional_code213_fifo.qip
convolutional_code213_fifo.v
convolutional_code213_fifo_bb.v
convolutional_decode.v
convolutional_decode.v.bak
decode_sample_mod.v
decode_sample_mod.v.bak
encode213.v
encode213.v.bak
EncodeDecode.jdi
EncodeDecode.qpf
EncodeDecode.qsf
EncodeDecode.qws
EncodeDecode_assignment_defaults.qdf
EncodeDecode_nativelink_simulation.rpt
FF1.rbf
lut_4bit_ones.v
lut_4bit_ones.v.bak
output_file.rbf
PLLJ_PLLSPE_INFO.txt
pllx4.ppf
pllx4.qip
pllx4.v
pllx4_bb.v
qmegawiz_errors_log.txt
rs_code.bsf
rs_code.html
rs_code.qip
rs_code.v
rs_code_bb.v
rs_code_block_period_stim.txt
rs_code_encoded_data.txt
rs_code_nativelink.tcl
rs_code_testbench.v
rs_code_vsim_script.tcl
speech_rx.v
speech_rx.v.bak
speech_rx_fifo.qip
speech_rx_fifo.v
speech_rx_fifo_bb.v
speech_tx.v
speech_tx.v.bak
SportConfigClient.v
SportConfigClient.v.bak
SportConfigClient_fifo.qip
SportConfigClient_fifo.v
SportConfigClient_fifo_bb.v
SportDataClient.v
SportDataClient.v.bak
SportDataClient_fifo.qip
SportDataClient_fifo.v
SportDataClient_fifo_bb.v
sport_ds_fifo.qip
sport_ds_fifo.v
sport_ds_fifo_bb.v
tcm_rcv_sector.txt
test.bsf
test.html
test.qip
test.v
test.vec
test_bb.v
test_cos_c.hex
test_cos_f.hex
test_model.m
test_nativelink.tcl
test_sin_c.hex
test_sin_f.hex
test_st.inc
test_st.v
test_tb.m
test_tb.v
test_tb.vhd
test_vho_msim.tcl
test_vo_msim.tcl
test_wave.do
transbit.txt
velocity.log
viterbi_decode.bsf
viterbi_decode.html
viterbi_decode.qip
viterbi_decode.v
viterbi_decode.v.err
viterbi_decode.xml
viterbi_decode_bb.v
viterbi_decode_nativelink.tcl
viterbi_decode_testbench.vhd
viterbi_decode_vsim_script.tcl
xx.bsf
xx.html
xx.qip
xx.v
xx.vo
xx_bb.v
xx_nativelink.tcl
xx_syn.v
xx_testbench.vhd
xx_vsim_script.tcl