资 源 简 介
采用Verilog HDL设计,在掌宇智能开发板上得到实现
根据抢答器的原理，整个电路可划分为三部分：采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on
the palm space intelligence development board to snatch the answering
principle, the entire electric circuit may divide is three parts: The
sampling electric circuit, the gate control the electric circuit and
the decoding circuit
文 件 列 表
qdq
decoder.acf
decoder.cnf
decoder.fit
decoder.hex
decoder.hif
decoder.mmf
decoder.ndb
decoder.pin
decoder.pof
decoder.rpt
decoder.scf
decoder.snf
decoder.sof
decoder.sym
decoder.ttf
decoder.v
LIB.DLS
qdq(1).cnf
qdq.acf
qdq.cnf
qdq.fit
qdq.gdf
qdq.hex
qdq.hif
qdq.mmf
qdq.ndb
qdq.pin
qdq.pof
qdq.rpt
qdq.scf
qdq.snf
qdq.sof
qdq.ttf
U1593729.DLS
操作和引脚说明.doc
