资 源 简 介
AjarDSP
AjarDSP (ajar as in slightly open) is an open source implementation of a synthesizable 16-bit dual-mac VLIW DSP with accompanying tools.
Background
The goal of the the AjarDSP project is to create a free open source
digital signal processor accompanied with a open source tool chain.
The DSP itself is intended to be simple, pure and reasonably small.
The design is cache-less and the DSP operates entirely on its internal
memories. Its primary purpose is SoC integration but it can also
operate stand alone. The DSP is designed to be of
the "16-bit dual-mac" class, meaning that the execution units and data
paths are dimensioned so that it can multiply and accumulate two
16-bit integer pairs every clock cycles as well as fetching four
16-bit operands from memory.
The AjarDSP core is implemented in synthesizeable Verilog HDL.
Why?
There are many open source CPU implementations floating around on the
net but most o
