资 源 简 介
1. 一位全加器设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY add IS
PORT(a,b,cin:IN STD_LOGIC;
Co,S:OUT STD_LOGIC);
END ENTITY add;
ARCHITECTURE fc1 OF add is
BEGIN
S<= a xor b xor cin; --这两个为推得的表达式
Co<= (a and b) or (a and cin) or (b and cin);
END ARCHITECTURE fc1;
