资 源 简 介
Project Abstract:
It is commonly known that accesses to off-chip resources, particularly memory, cause considerable
performance limitations in computing systems. To speed up memory access it is necessary to design
high frequency chip-to-chip interconnects. These high frequency connections introduce many second
order effects that make bit sampling difficult. It is proposed that current signal analysis techniques
are researched and used to develop a software tool that interconnect designers can use to obtain
design validation of a given interconnect with a fixed sampling window. It is expected that such a
tool will allow designers to develop faster and lossless interconnects.
Team Members:
Bryson Kent - u0553461(AT)utah.edu
Ben Meakin - ben.meakin(AT)utah.edu
Jordan Kemp - jordan.kemp(AT)utah.edu
M. Lucas Loero - u0527079(AT)utah.edu
Raheem Alhamdani - R.Alhamdani(AT)utah.edu
