资 源 简 介
在3DIC設計中會使用的方法
Floorplanning is an important and dispensable stage in the traditional integrated circuit design process. With the raised module numbers and increased wire length, the computation complexity is raised dramatically. Obviously, the traditional algorithms need to be updated. We developed an orthogonal table, in which each factor represents a module and the level of a specified factor denotes the orientation of that module. With this orthogonal table, the solution space is significantly decreased.
We use sequence pair to represent a floorplan and the fast longest common subsequence is used accordingly to calculate the area of
