文 件 列 表
Example-b8-2
pll_ram
timing_sim
work
func_sim
source
Altera_lib_files
示例说明.doc
Example-b8-1
pll_ram
func_sim
timing_sim
source
Altera_lib_files
示例说明.doc
Example-b8-5
demo_project
work
test_counter
Source
示例说明.doc
demo_project
work
Example-b8-3
work
counter
示例说明.doc
counter.do
stimulus.do
counter.v
vsim.wlf
Example-b8-6
Synplify_Pro
source
mixed
vhdl
示例说明.doc
Synplify_Pro
source
VHDL
Example-b4-2
Solution
Simulation
Project
示例说明.doc
Solution
Example-b4-1
Solution
Simulation
Project
示例说明.doc
Example-b8-4
示例说明.doc
gold_sim.do
sec_sim.do
beh_sram.v
sm.v
sm_seq.v
test_sm.v
Example-b3-1
uart_regs
示例说明.doc
光盘使用说明.doc
