资 源 简 介
Verilog 下 16位除法算法程序，高精度，固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles
文 件 列 表
double_subc
double_subc_16bits(1).cnf
double_subc_16bits(10).cnf
double_subc_16bits(11).cnf
double_subc_16bits(12).cnf
double_subc_16bits(13).cnf
double_subc_16bits(14).cnf
double_subc_16bits(15).cnf
double_subc_16bits(16).cnf
double_subc_16bits(2).cnf
double_subc_16bits(3).cnf
double_subc_16bits(4).cnf
double_subc_16bits(5).cnf
double_subc_16bits(6).cnf
double_subc_16bits(7).cnf
double_subc_16bits(8).cnf
double_subc_16bits(9).cnf
double_subc_16bits.acf
double_subc_16bits.cnf
double_subc_16bits.fit
double_subc_16bits.hex
double_subc_16bits.hif
double_subc_16bits.mmf
double_subc_16bits.ndb
double_subc_16bits.pin
double_subc_16bits.pof
double_subc_16bits.rpt
double_subc_16bits.scf
double_subc_16bits.snf
double_subc_16bits.sof
double_subc_16bits.ttf
double_subc_16bits.v
LIB.DLS
U5852470.DLS
U8127845.DLS
