一个用VHDL语言编写的全加器，是数字电路EDA设计的一个例子，可能不太特别，但是应该可以用一下的。-a VHDL prepared by the full adder, digital circuit design of an EDA example, may not be special, but should be able to use what they are doing.
SHOW FULL COLUMNS FROM `jrk_downrecords` [ RunTime:0.001889s ]
SELECT `a`.`aid`,`a`.`title`,`a`.`create_time`,`m`.`username` FROM `jrk_downrecords` `a` INNER JOIN `jrk_member` `m` ON `a`.`uid`=`m`.`id` WHERE `a`.`status` = 1 GROUP BY `a`.`aid` ORDER BY `a`.`create_time` DESC LIMIT 10 [ RunTime:0.085119s ]
SHOW FULL COLUMNS FROM `jrk_tagrecords` [ RunTime:0.002318s ]
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SHOW FULL COLUMNS FROM `jrk_member` [ RunTime:0.002104s ]
SELECT `id`,`username`,`userhead`,`usertime` FROM `jrk_member` WHERE `status` = 1 ORDER BY `usertime` DESC LIMIT 10 [ RunTime:0.003533s ]
SHOW FULL COLUMNS FROM `jrk_searchrecords` [ RunTime:0.002076s ]
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SELECT aid,title,count(aid) as c FROM `jrk_downrecords` GROUP BY `aid` ORDER BY `c` DESC LIMIT 10 [ RunTime:0.014383s ]
SHOW FULL COLUMNS FROM `jrk_articles` [ RunTime:0.002234s ]
UPDATE `jrk_articles` SET `hits` = 1 WHERE `id` = 233194 [ RunTime:0.001070s ]
