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您现在的位置是:虫虫源码 > 其他 > HDLC接口协议的FPGA实现使用verilog

HDLC接口协议的FPGA实现使用verilog

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HDLC接口协议的FPGA实现使用verilog-design of HDLC

文 件 列 表

hdlc
utility
hdlc
db
FlagDetect.vhd
flag_ins.vhd
hdlc_top.asm.rpt
hdlc_top.done
hdlc_top.fit.rpt
hdlc_top.fit.smsg
hdlc_top.fit.summary
hdlc_top.flow.rpt
hdlc_top.map.rpt
hdlc_top.map.summary
hdlc_top.pin
hdlc_top.pof
hdlc_top.qpf
hdlc_top.qsf
hdlc_top.qws
hdlc_top.sof
hdlc_top.sta.rpt
hdlc_top.sta.summary
hdlc_top.vhd
local_if.vhd
rxbuff.vhd
rxbuff.vhd.bak
rxchannel.vhd
rxcont.vhd
rxfcs.vhd
rxsynch.vhd
rx_fifo10x1024.bsf
rx_fifo10x1024.cmp
rx_fifo10x1024.inc
rx_fifo10x1024.qip
rx_fifo10x1024.v
rx_fifo10x1024_bb.v
rx_fifo10x1024_wave0.jpg
rx_fifo10x1024_wave1.jpg
rx_fifo10x1024_waveforms.html
txbuff.vhd
txbuff.vhd.bak
txchannel.vhd
txcont.vhd
txfcs.vhd
txsynch.vhd
tx_fifo10x1024.bsf
tx_fifo10x1024.cmp
tx_fifo10x1024.inc
tx_fifo10x1024.qip
tx_fifo10x1024.vhd
tx_fifo10x1024_wave0.jpg
tx_fifo10x1024_wave1.jpg
tx_fifo10x1024_waveforms.html
tx_fifo8x1024.bsf
tx_fifo8x1024.cmp
tx_fifo8x1024.inc
tx_fifo8x1024.qip
tx_fifo8x1024.vhd
tx_fifo8x1024_wave0.jpg
tx_fifo8x1024_wave1.jpg
tx_fifo8x1024_waveforms.html
ZeroDetect.vhd
zeroins.vhd
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