verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
SHOW FULL COLUMNS FROM `jrk_downrecords` [ RunTime:0.001225s ]
SELECT `a`.`aid`,`a`.`title`,`a`.`create_time`,`m`.`username` FROM `jrk_downrecords` `a` INNER JOIN `jrk_member` `m` ON `a`.`uid`=`m`.`id` WHERE `a`.`status` = 1 GROUP BY `a`.`aid` ORDER BY `a`.`create_time` DESC LIMIT 10 [ RunTime:0.091539s ]
SHOW FULL COLUMNS FROM `jrk_tagrecords` [ RunTime:0.001205s ]
SELECT * FROM `jrk_tagrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 20 [ RunTime:0.001921s ]
SHOW FULL COLUMNS FROM `jrk_member` [ RunTime:0.001300s ]
SELECT `id`,`username`,`userhead`,`usertime` FROM `jrk_member` WHERE `status` = 1 ORDER BY `usertime` DESC LIMIT 10 [ RunTime:0.003738s ]
SHOW FULL COLUMNS FROM `jrk_searchrecords` [ RunTime:0.001081s ]
SELECT * FROM `jrk_searchrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 5 [ RunTime:0.003188s ]
SELECT aid,title,count(aid) as c FROM `jrk_downrecords` GROUP BY `aid` ORDER BY `c` DESC LIMIT 10 [ RunTime:0.020564s ]
SHOW FULL COLUMNS FROM `jrk_articles` [ RunTime:0.001468s ]
UPDATE `jrk_articles` SET `hits` = 1 WHERE `id` = 226838 [ RunTime:0.001255s ]
