资 源 简 介
应用背景Abstract—Leros is a tiny microcontroller that is optimized for
current low-cost FPGAs. Leros is designed with a balanced logic
to on-chip memory relation. The design goal is a microcontroller
that can be clocked in about half of the speed a pipelined on-chip
memory and consuming less than 300 logic cells.
The architecture, which follows from the design goals, is a
pipelined 16-bit accumulator processor. An implementation of
Leros needs at least one on-chip memory block and a few hundred
logic cells.
The application areas of Leros are twofold: First, it can be used
as an intelligent peripheral device for auxiliary functions in an
FPGA based system-on-chip design. Second, the very small size
of Leros makes it an attractive softcore for many-core research
with low-cost FPGAs.关键技术The smallest core is comparable to Leros and can be implemented<
