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FPGA 全数字化实现信号发生器

  • 资源大小:32.52 MB
  • 上传时间:2021-06-30
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  • 资源积分:1积分
  • 标      签: Verilog

资 源 简 介

FPGA 全数字化实现信号发生器,产生正弦、三角、方波;幅值频率可调

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xinhaofasheng
DDS.bdf
DDS.bsf
DDS.cdf
DDS.vwf
adder15b.bsf
adder15b.vhd
adder15b.vhd.bak
comparator_10.bsf
comparator_10.v
comparator_10.v.bak
control.bsf
control.v
control.v.bak
db
decorder84.bsf
decorder84.v
decorder84.v.bak
div12.bsf
div12.v
fangbo.mif
fangbo.qip
fangbo.v
fangbo.v.bak
fangbo_bb.qip
fangbo_bb.v
fangbogen.bsf
fangbogen.v
fangbogen.vwf
greybox_tmp
incremental_db
keybin.bsf
keybin.v
keybin.v.bak
monidds.bdf
mux3_1.bsf
mux3_1.v
mux3_1.v.bak
output_file.map
output_file.pof
output_files
reg15b.bsf
reg15b.vhd
reg15b.vhd.bak
remote_rcv.bsf
remote_rcv.v
rom_1p.qip
rom_1p.v
rom_1p.v.bak
rom_1p_bb.qip
rom_1p_bb.v
rom_1p_bb.v.bak
rom_1p_bb_bb.v
rom_1zx.qip
rom_1zx.v
rom_1zx_bb.v
sabjiao_2.bdf
sabjiao_2.bsf
sanjiao.mif
sanjiao.qip
sanjiao.v
sanjiao.v.bak
sanjiao_bb.v
sanjiaogen.bsf
sanjiaogen.v
sanjiaogen.v.bak
sanjiaogen.vwf
simulation
sin1010.mif
sing_1.bdf
sing_1.dpf
sing_1.qpf
sing_1.qsf
sing_1.qws
sing_1_description.txt
sing_1_nativelink_simulation.rpt
singen.bsf
singen.v
singen.v.bak
singen.vwf
suocunqi.bsf
suocunqi.v
suocunqi.v.bak
yaokongqi.bdf
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