资 源 简 介
用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
文 件 列 表
time24
work
_ngo
xst
_xmsgs
time24.v
time60.v
time_go.v
sec60.v
time24.ise
time_tst_bencher.prj
time_tst.xwv
time_tst.xwv_bak
time_tst.tfw
time_tst.ant
time_tst.tbw
time_tst.jhd
time24.ise_ISE_Backup
vsim.wlf
results.txt
time_going.prj
time_going.lso
time_going.xst
time_going.cmd_log
time_going.syr
time_going_vhdl.prj
time_going.ngr
time_going.ngc
time_going.stx
time_going.bld
time_going.ngd
time_going.ucf
time_going.cel
time_going.lfp
time_going_summary.html
modelsim.ini
time24.ise_8.1i_backup
