用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试
-Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
SHOW FULL COLUMNS FROM `jrk_downrecords` [ RunTime:0.001378s ]
SELECT `a`.`aid`,`a`.`title`,`a`.`create_time`,`m`.`username` FROM `jrk_downrecords` `a` INNER JOIN `jrk_member` `m` ON `a`.`uid`=`m`.`id` WHERE `a`.`status` = 1 GROUP BY `a`.`aid` ORDER BY `a`.`create_time` DESC LIMIT 10 [ RunTime:0.092273s ]
SHOW FULL COLUMNS FROM `jrk_tagrecords` [ RunTime:0.001215s ]
SELECT * FROM `jrk_tagrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 20 [ RunTime:0.001964s ]
SHOW FULL COLUMNS FROM `jrk_member` [ RunTime:0.001162s ]
SELECT `id`,`username`,`userhead`,`usertime` FROM `jrk_member` WHERE `status` = 1 ORDER BY `usertime` DESC LIMIT 10 [ RunTime:0.003666s ]
SHOW FULL COLUMNS FROM `jrk_searchrecords` [ RunTime:0.001019s ]
SELECT * FROM `jrk_searchrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 5 [ RunTime:0.003290s ]
SELECT aid,title,count(aid) as c FROM `jrk_downrecords` GROUP BY `aid` ORDER BY `c` DESC LIMIT 10 [ RunTime:0.015463s ]
SHOW FULL COLUMNS FROM `jrk_articles` [ RunTime:0.001398s ]
UPDATE `jrk_articles` SET `hits` = 1 WHERE `id` = 144672 [ RunTime:0.001439s ]
