资 源 简 介
32×32的寄存器堆，它有32个32位的寄存器、两个读端口和一个写端口。该寄存器堆由3个层次共5个模块构成，最低层次的模块是D触发器，中间层次的模块包括32位寄存器、5位地址译码器、32选1多路选通器，顶层模块是寄存器堆模块。设计采用行为建模和结构建模相结合的方法，先用行为建模方法建立低层模块，然后再用结构建模方法搭建高层模块。-32 × 32 of the register file, it has 32 32-bit registers, two read ports and one write port. The register file by the three levels of a total of five modules, the lowest level module is the D flip-flop, middle-level module including 32-bit register, address decoder 5, 32 election more than one way strobe, and top-level module is Register File module. Design using behavioral modeling and structural modeling method of combining the first act of modeling methods used to establish low-level modules, then the structural modeling method to build high-level module.
