资 源 简 介
嵌入式可编程器件CPLD的典型实例 压缩包，共计43个源码文件。 使用ALTERA的 Muxplus 软件即可编辑仿真 相关软件可在教育网ftp下载[天网查询，有很多站点提供]-Embedded Programmable CPLD in a typical example of compressed, for a total of 43 source document. Altera Muxplus use the software can edit simulation software available from the Education Network ftp download [days Web inquiries, many sites provide]
文 件 列 表
图像所verilog实例 【46】
ADC_16bit.v
adder_8bit.v
adder_8bit_2.v
ALL.V
binarytogray.v
cla_8bits.v
COMPARE.V
dds.v
DECODER1.V
decoder3x8.v
div16.v
encoder8x3.v
encoder8x3_2.v
fifo.v
fifo_16x16.v
FIFO_2.V
framer.v
frequency5x2.v
full_adder_1.v
full_adder_2.v
gencrc.v.txt
half_adder_1.v
half_adder_2.v
half_adder_3.v
lead_8bits_adder.v
lead_8bits_adder2.v
MUL16.V
mult16.v
multi_select_1.v
mult_piped_8x8.v
mult_select.v
MUX8X8.V
myrand.c
nco.v
onehot.v
pic.v
PLI.TAR
RISC8.ZIP
sequence_dectect.v
SHIFTER.V
string.v
SYNTHPIC.ZIP
TEST.V
testing.v.txt
test_cla_8bits.v
wpulse.v.txt
