基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
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第6章 time_mux time_disp_select time_auto_and_set timeset timepiece stopwatch maincontrol main fdiv disp_select disp_data_mux date alarmclock
SHOW FULL COLUMNS FROM `jrk_downrecords` [ RunTime:0.001282s ]
SELECT `a`.`aid`,`a`.`title`,`a`.`create_time`,`m`.`username` FROM `jrk_downrecords` `a` INNER JOIN `jrk_member` `m` ON `a`.`uid`=`m`.`id` WHERE `a`.`status` = 1 GROUP BY `a`.`aid` ORDER BY `a`.`create_time` DESC LIMIT 10 [ RunTime:0.087627s ]
SHOW FULL COLUMNS FROM `jrk_tagrecords` [ RunTime:0.001199s ]
SELECT * FROM `jrk_tagrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 20 [ RunTime:0.002259s ]
SHOW FULL COLUMNS FROM `jrk_member` [ RunTime:0.001269s ]
SELECT `id`,`username`,`userhead`,`usertime` FROM `jrk_member` WHERE `status` = 1 ORDER BY `usertime` DESC LIMIT 10 [ RunTime:0.003897s ]
SHOW FULL COLUMNS FROM `jrk_searchrecords` [ RunTime:0.001024s ]
SELECT * FROM `jrk_searchrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 5 [ RunTime:0.003325s ]
SELECT aid,title,count(aid) as c FROM `jrk_downrecords` GROUP BY `aid` ORDER BY `c` DESC LIMIT 10 [ RunTime:0.016425s ]
SHOW FULL COLUMNS FROM `jrk_articles` [ RunTime:0.001299s ]
UPDATE `jrk_articles` SET `hits` = 1 WHERE `id` = 108551 [ RunTime:0.001330s ]
